1. Field of the Invention
This invention relates to a fitting substrate for connection to which a plurality of signal processing substrates is fitted. For instance, the invention relates to a fitting substrate for connection that will be suitable for use in a disk array control apparatus, or the like.
2. Description of the Related Art
In an electronic appliance such as a disk control apparatus, for example, a plurality of signal processing substrates is fitted to accomplish respective functions. Known examples of such signal processing substrates include a memory substrate having cache memories and shared memories mounted thereto, a bus switch substrate for controlling access to the memory substrate and an adaptor substrate for gaining access to the memory substrate through the bus switch substrate and reading and writing data. The adaptor substrate is used for transmitting and receiving data to and from a host computer and a disk apparatus. These signal processing substrates are respectively fitted to a fitting substrate for connection that is referred to as a “back plane”. Each signal processing substrate is electrically connected through printed wires formed on the back plane. According to a known technology, for example, a plurality of printed substrates is fitted to each surface of a back panel and both printed substrates are connected to each other through printed wires formed on the back panel (JP-A-11-312854).
The bus switch substrate on the data reception side is connected to a plurality of adaptor substrates (a plurality of host adaptor substrates and a plurality of disk adaptor substrates). Therefore, signal pins of the connector to which the bus switch substrate is fitted are divided into groups each corresponding to each adaptor substrate. On the other hand, each adaptor substrate on the data transmission side has a common interface. Therefore, the arrangement of the signal pins of the connector to which each adaptor substrate is fitted is in common.
As described above, the positions of the signal pins are different between the data reception side (bus switch substrate) and the data transmission side (adaptor substrate) that are to be mutually connected. Therefore, printed wiring for mutually connecting the corresponding signal pins is formed in such a fashion that a wiring direction can be changed appropriately inside the back plane. According to the known technology, therefore, the printed wiring is formed in the bent form in many cases and curve points develop in the printed wiring. Radiation noise is likely to occur at the curve point. Because impedance changes with the change of the line width at the curve point, reflection of signals is likely to occur, too. When the curve point exists in the printed wiring, signal quality is likely to drop. Particularly because a disk array control apparatus controls high-speed data communication made between a disk apparatus and a host computer, influences of the curve points of the printing wiring on the drop of quality of high-speed data communication are great.
The reason why the curve point occurs in the printed wiring will be explained with reference to FIGS. 10 to 13.
FIG. 10 is an enlarged schematic perspective view of a part of the disk array control apparatus. A large number of connectors 501 are disposed on the front surface side of a back plane 500 constituted as a multi-layered printed substrate. The back plane 500 is put perpendicularly (in a Z direction) inside a control box (not shown). A plurality of rows of connectors 501 extending in the Z direction is arranged in an X direction with gaps among them. A plurality of various kinds of substrates 510 and 520 is fitted to the back plane 500, respectively.
One kind 510 of the substrates is an adaptor substrate for transmitting and receiving data to and from a host computer or a disk apparatus, for example. The adaptor substrate connected to the host computer is also referred to as a “host adaptor substrate” or a “channel adaptor substrate”. The adaptor substrate connected to the disk apparatus is called a “disk adaptor substrate”. The host adaptor substrate and the disk adaptor substrate have the same interface structure and their signal pin arrangement is the same, too. Therefore, both of them will be generically called hereinafter the “adaptor substrate 510”.
The other substrate 520 is a bus switch substrate (that may be called also “switch control substrate”) for controlling connection with a cache memory substrate or a shared memory substrate (both of which are not shown in the drawing). The bus switch substrate for controlling connection with the cache memory substrate switch substrate is called a “cache memory bus switch substrate” and the bus switch substrate for controlling connection with the shared memory substrate is called a “shared memory bus switch substrate”. Therefore, they are altogether called hereby the “bus switch substrate 520”.
Each adaptor substrate 510 is connected to each bus switch substrate 520. Therefore, the signals outputted from a signal processing LSI 511 of each adaptor substrate 510 are gathered for each bus switch substrate 520 as the connection destination as represented by path groups PG11 to PG14. Similarly, each bus switch substrate 520, too, is connected to each adaptor substrate 510. Therefore, the signals outputted from a signal processing LSI 521 of each bus switch substrate 520 are gathered for each adaptor substrate 510 as the connection destination as represented by path groups PG21 to PG24.
The output positions of the signals from each of the LSI 511 and 521 extend in the arranging direction (Z direction) of the respective connectors 512 and 522 so as to easily accomplish equidistant wiring inside each of the adaptor substrate 510 and the bus switch substrate 520. The arrangement of the signal pins of the connector 512 of each adaptor substrate 510 is the same. Here, the connector 512 of each adaptor substrate 510 and the connector 522 of each bus switch substrate 520 serially correspond to one another from the upper side. Therefore, when the signal pins of a plurality of adaptor substrates 510 and the corresponding signal pins of the bus switch substrates 520 adjacent to the former in the X direction are connected, adjustment in the Z direction becomes necessary. This adjustment in the Z direction generates the curve points in the printed wiring.
As shown in FIG. 11, the data path group taken out at the uppermost part of the first adaptor substrate 510-1 in the Z direction is connected to the uppermost signal connector 522 of the bus switch substrate 520 from the uppermost connector of the signal connector 512-1 in the Z direction through the printed wiring of the back plane 500. Next, let's consider the first adaptor substrate 510-1 and the second adaptor substrate 510-2 adjacent to the former in the X direction. Then, the data path taken out at the uppermost part of the second adaptor substrate 510-2 in the Z direction is connected to the connector just below the uppermost signal connector of the bus switch substrate 520 in the Z direction. Because each of the adaptor substrates 510-1 and 510-2 has the same signal arrangement, the printed wiring must be adjusted in the Z direction on the back plane 500 in order to connect them to the same bus switch substrate 520.
FIG. 12 shows in partial enlargement the mode of connecting N adaptor substrates 510 and M bus switch substrates 520 (only one of which is shown in the drawing) through the printed wiring of the back plane 500. FIG. 12 shows the connectors of each substrate. Connectors 512-11 to 512-NM are fitted to the N adaptor substrates 510. The first bus switch substrate 520 is shown fitted to the connectors 522-11 to 522-1N on the right side in the drawing. Here, the suffix allocated to the reference numeral of each connector will be explained. The numeral of the first digit after the hyphen represents the substrate number and the numeral of the second digit represents the data path group number. Therefore, the connector 512-11 represents the connector corresponding to the first data path group of the first adaptor substrate 510. Similarly, the connector 512-NM represents the connector corresponding to the Mth data path group of the Nth adaptor substrate 510. This also holds true of the connector 522 of the bus switch substrate 520. Only one row of the connectors for the bus switch substrate is shown for the sake of explanation and reference numeral 522-MN is allocated to the connector corresponding to the Nth data path group of the Mth bus switch substrate 520.
N adaptor substrates 510 are connected to M bus switch substrates 520, respectively. Therefore, in the case of the connectors 512-11 to 512-1M for the first adaptor substrate, the first connector 512-11 is connected to the connector 522-11 for the first bus switch substrate. The second connector 512-12 is connected to the second bus switch substrate 522-21 (not shown). Similarly, the connectors 511-1 to 511-1N for the first adaptor substrate are connected to the connectors 522-11 to 522-M1 (not shown other than 522-11) for all the bus switch substrates, respectively. Let's consider the connectors 512-21 to 512-2M for the second adaptor substrate. The first connector 512-21 is connected to the connector 522-12 for the first bus switch substrate and the connector 512-22 for the second adaptor substrate is connected to the connector 522-22 (not shown) for the second bus switch substrate. Similarly, the connectors 522-21 to 522-2M for the second adaptor substrate are connected to the connectors 522-22 to 522-M2 for all the bus switch substrates, respectively. This also holds true of the connectors (512-31 to 512-3M) to (512-N1 to 512-NM) (only apart of which is shown) for the third to Nth adaptor substrates.
A concrete wiring method will be explained. The arrangement of the signal pins of the connectors for the adaptor substrates are set to the (X, Y) coordinates and the pin number, to (Xa, Za). The first connector 512-11 positioned at the uppermost position of the connector for the first adaptor substrate has the signal pins at the coordinates (1, 1) to the coordinates (X1a, Z1a). On the other hand, the signal pins of the connector for the bus switch substrate start from the coordinates (1, 1) and end up with the coordinates (Xb, Zb).
The case where the signal pins of the data path group of the connector 512-11 for the adaptor substrate are connected to the signal pins of the connector 522-11 for the bus switch substrate will be first explained in detail. To begin with, the signal pin positioned at the coordinates (1, 1) of the connector 512-11 for the adaptor substrate is connected to the signal pin positioned at the coordinates (1, 1) of the connector 522-11 for the bus switch substrate. In this case, the wire is taken out at an angle of 45 degrees in a Z1-X1 direction (right downward direction in the drawing) lest the printed wiring pattern come into contact with each through-hole clearance of the second signal pin (2, 1) et seq to (Xa, 1) in the X axis direction. The wire is then extended in the X1 direction to a position in the proximity of the signal pin positioned at the coordinates (1, 1) of the connector 522-11 for the bus switch substrate at the position where the printing wiring pattern does not contact with the each through-hole clearance provided above and below the Z-direction. The end of the wire is bent at 450 in an X1-Z2 direction (right upward direction in the drawing) and is connected to the signal pin (1, 1) of the connector 522-11 for the bus switch substrate. In other words, the printed wire is extended in the horizontal direction (X direction) by selecting a position not interfering with each through-hole clearance, and is bent at 45° and connected to the signal pins on the sides of both start and terminal ends. Thereafter, each signal pin of the connector 512-11 for the adaptor substrate is connected in the same way to each corresponding signal pin of the connector 522-11 for the bus switch substrate.
Here, because the gap between the signal pins and the wiring width are limited, only a predetermined number T of wiring patterns can be passed through each through-hole clearance. The explanation will be given hereby about the case of T=2. In the case of the signal pin positioned at an odd-numbered (2n+1)th position in the Z direction, the wiring is taken out from below (on the Z2 side) of this signal pin. As to the signal pin positioned at an even-numbered (2n)th position in the Z direction, the wire is taken out from above (on the Z1 side) of this signal pin. The first to Zlath, in the Z direction, (represented as Za in the drawing) signal pins constituting the row of (X coordinates=1) area 11 wired by the method described above. Next, the signal pins constituting the X coordinates=2 are similarly connected to the corresponding signal pins of the connector 522-11 for the bus switch substrate. Here, because the wire for connecting each signal pin of the row of the X coordinates=1 has already been passed through the gap of the signal pins constituting the row of the X coordinates=2, connection must be so made as to avoid this wire. In the row of the X coordinates=2, therefore, the signal pin positioned at an odd-numbered (2n+1)th position in the Z direction is so wired as to pass above this signal pin and the signal pin positioned at an even-numbered (2n) th position in the Z direction is so wired as to pass below this signal pin, on the contrary to the row of the X coordinates=1.
Next, wiring is made for each signal pin constituting the row of the X coordinates=3. However, because the wires for connecting the signal pins constituting the rows of the X coordinates=1 and the X coordinates=2 have already been arranged, wiring cannot be made on the same plane. Therefore, as to the signal pins constituting the rows of the X coordinates=3 and the X coordinates=4, another layer different from the wiring layer used for wiring the signal pins constituting the rows of the X coordinates=1 and the X coordinates=2 is used. Thereafter, whenever the value of the X coordinates assumes an odd number (X=2n+1), the wiring layer is changed. In this way, the printed wiring pattern is set so that all the signal pins of the connector 512-11 for the adaptor substrate can be connected to the corresponding signal pins of the connector 522-11 for the bus switch substrate.
The wiring pattern for connecting the signal pins of the connector for each adaptor substrate to the signal pins of the connector for the bus switch substrate is thereafter set similarly. Because the Z direction coordinates of the corresponding connectors are different as also shown in enlargement in FIG. 7, most of the wires taken out from the connectors for the adaptor substrates are taken out in the X direction, are then bent in the Z direction, again extend in the X direction and are connected to the connectors for the bus switch substrates. In other words, a Z direction adjustment region 600 must be secured in advance so that each printed wiring can extend in the Z direction. Consequently, a plurality of curve points occurs in each printed wiring and results in deterioration of signal quality. Because a predetermined clearance must also be secured between the wires, the width of the Z direction adjustment region 600 becomes greater with the increase of the number of wires. The greater the number of the substrates to be fitted to the back plane 500 is, the greater becomes the area of the back plane 500 and the size of the casing of the apparatus. Nonetheless, the market strongly needs a smaller disk array system having higher performance due to the limited size of the mounting space. To achieve higher performance, the number of substrates connected to the back plane 500 must be increased but the increase of the number of substrates invites the increase of the size of the casing of the apparatus. The prior art technology thus has a tradeoff relation between the reduction of the size of the apparatus and higher performance.